The present invention relates to a two-dimensionally arrayed solid-state imaging device having a photodiode array arranged at a photo-sensing section and a charge transfer device (CTD) such as a BCD, CCD or BBD as a readout horizontal register.
FIG. 1 shows an example of a photo-sensor having a diode array arranged at a photo-sensing section and a CTD as a readout register. FIG. 1 corresponds to FIG. 5 of U.S. Ser. No. 462,763, and, as noted in U.S. Ser. No. 462,763, represents earlier work unpublished as of the time of filing for the same assignee as in the present case. In FIG. 1, numeral 1 denotes photodiodes, numeral 2 denotes vertical switching MOS transistors (insulated gate type field effect transistors), numeral 3 denotes a vertical scanning circuit, numeral 4 denotes vertical signal lines, numerals 5 (5'), 11 (11') and 6 (6') denote gate MOS transistors, numeral 7 (7') denotes an output amplifier, numeral 8 (8') denotes a CTD which functions as a horizontal register, numeral 9 (9') denotes a CTD input circuit, and numeral 10 (10') denotes a blooming suppression circuit. The CTD 8 is usually driven in two phases, three phases or quasi-four phases. The CTD may be a BCD (bulk charge transfer device), a CCD (charge coupled device) or BBD (bucket brigade device). Quasi-signals such as blooming and vertical smear stored on the vertical signal lines 4 in a horizontal scanning period are swept out through the gates 5, 11 and 10 at a beginning of a horizontal blanking period. Thereafter, a horizontal line of picture cells shown by .circle.a in FIG. 1 are selected and one line of signals are transferred in a unit to the channel .circle.A CTD register 8, and stored in respective memory areas.
The above operation is carried out in a first half of the horizontal blanking period, and in a second half period one horizontal line of signals of the photodiodes shown by .circle.b in FIG. 1 are transferred to and stored in the channel .circle.B CTD register 8'. During the horizontal scanning period, the gates 6 and 6' are turned off and the CTD is driven to simultaneously read out the two lines of signals from the output amplifiers 7 and 7'. The two lines of signals are simultaneously read out in order to enhance a resolution of an image of a single-plate or substrate color sensor.
The imaging device of FIG. 1 has the following disadvantage. A transfer efficiency .eta. from the vertical signal line 4 to the horizontal register 8 is low and the transfer efficiency varies from line to line. As a result, a fixed pattern noise is produced. The transfer efficiency .eta. is represented by a product of a transfer efficiency .eta..sub.1 from the vertical signal line 4 to a point 12 in FIG. 1 through the transistor 5 and a transfer efficiency .eta..sub.2 from the point 12 to the CTD 8. The transfer efficiency .eta..sub.1 through the transistor 5 is approximated by ##EQU1## where t is a charge transfer time and T is defined by ##EQU2## where .beta. is a channel conductance of the transistor 5, C.sub.V is a capacitance per line of the vertical signal lines and q.sub.o is a transfer charge. In order to increase the transfer efficiency, the conductance .beta. of the transistor 5 may be increased or the capacitance C.sub.V of the vertical signal line 4 may be reduced. However, the capacitance C.sub.V of the vertical signal line is essentially determined by a manufacturing technique and it only has a small degree of freedom of design.
As an approach to increase the conductance of a transistor in order to increase the charge transfer efficiency, a method shown in FIG. 2 has been known. (See, for example, IEEE Vol. SC-12, No. 3, page 232 (1977), "J. Solid-State Circuits" by Jespers et al.) In the proposed circuit, a signal of a MOS-type imaging device is amplified by the circuit shown in FIG. 2 which is packaged on the same chip as the imaging device. (See FIG. 4) In FIG. 2, numeral 20 denotes a transfer transistor, numeral 21 denotes an inverter having a gain G, numerals 22 and 23 denote source and drain capacitances, numeral 24 denotes an inverter reference potential input terminal, numerals 25 and 29 denote a reset transistor and a gate thereof, numeral 26 denotes an output transistor, numeral 28 denotes a drain and numeral 27 denotes an output terminal. An effective conductance .beta..sub.eff of the transfer transistor 20 of the circuit of FIG. 2 is increased by the inverter 21 having the gain G as follows: EQU .beta..sub.eff =(1+G).sup.2 .multidot..beta. (3)
Accordingly, the charge transfer efficiency .eta. can be significantly increased. FIG. 3 shows a specific circuit therefor. However, the inventors of the present invention have found that the above circuit has problems with respect to a tailing characteristic of the transfer transistor and a random noise of the system.